The present invention relates to a semiconductor device formed on an SOS (Silicon On Sapphire) substrate.
There has heretofore been known a so-called SOI integrated circuit wherein an SOI (Silicon On Insulator) substrate formed by laminating a monocrystal silicon layer on an insulator is used and an elemental device such as a transistor is formed in the monocrystal silicon layer (refer to, for example, Japanese Unexamined Patent Publication No. Hei 5(1993)-326692).
The SOI integrated circuit is excellent in that as compared with an integrated circuit (hereinafter called a “silicon integrated circuit”) fabricated in a single silicon substrate, (1) it is less reduced in parasitic capacitance and excellent in high-speed property, (2) it is resistant to soft errors, (3) there is no latch up, and (4) a well process can be omitted.
There has been known a so-called SOS integrated circuit as a type of SOI integrated circuit. The SOS integrated circuit is of an integrated circuit formed in an SOS substrate wherein a monocrystal silicon layer is epitaxially grown on a sapphire substrate used as an insulator. In addition to the advantages brought about by the above SOI integrated circuit, the SOS integrated circuit has an advantage that noise via the substrate is less reduced because the sapphire substrate is thick (refer to, for example, Japanese Unexamined Patent Publication No. Hei 8(1996)-512432).
However, the SOS integrated circuit involves essential problems that stem from its structure. The first point resides in that a lattice mismatch of about 10% exists between a lattice constant of a sapphire monocrystal and a lattice constant of a silicon monocrystal at room temperature. The second point resides in that the sapphire monocrystal is larger 60% than the silicon monocrystal in thermal expansion coefficient.
Therefore, inter-atomic distances in crystal lattices of the silicon monocrystal and the sapphire monocrystal are nearly equal at a temperature (approximately 1000° C.) at the time of epitaxial growth of the monocrystal silicon layer. With cooling subsequent to the epitaxial growth, however, the sapphire monocrystal is shrunk in a greater degree than the silicon monocrystal. As a result, large compression stress occurs in the monocrystal silicon layer.
The mobility of electrons in a stress direction in the monocrystal silicon layer is reduced at the rate of 30% to 40% due to the compression stress. Therefore, when an n channel MOS field effect transistor with electrons as carriers is formed in the monocrystal silicon layer, a source-to-drain current (saturation drain current) is reduced.
Several techniques applicable for solving a problem about the compression stress applied to the monocrystal silicon layer in the SOS substrate have been disclosed.
The first conventional technique relates to a technique for growing a monocrystal GaN layer on a sapphire substrate. In a manner similar to the silicon monocrystal, the GaN monocrystal is also smaller than the sapphire monocrystal in thermal expansion coefficient, and a difference of about 13% occurs between lattice constants of the two at room temperature. Therefore, strong compression stress occurs in the monocrystal GaN layer deposited on the sapphire substrate at room temperature. The first conventional technique intends to grow a layer made up of GaN or the like on the back surface (surface on the non-deposition side of the monocrystal GaN layer) of the sapphire substrate as a stress cancellation layer (refer to, for example, FIG. 1 of Japanese Unexamined Patent Publication No. 2003-113000).
The second conventional technique relates to a silicon integrated circuit. In order to relax compression stress in the direction parallel to a substrate surface concerned with a channel region of an n-MOSFET, the entire n-MOSFET is covered with an SiN film having tensile stress (refer to, for example, FIG. 1 of Japanese Unexamined Patent Publication No. 2003-60076).